Flash memory devices, a type of non-volatile memory devices, have been known for many years. A flash memory device includes an array of memory cells, where each memory cell is implemented by a semiconductor transistor that typically has a floating gate region, a drain region, and a source region. A memory cell can have two or more distinct states which are implemented by controlling the amount of charge stored within the floating gate. That is, each state is associated with a different amount of charge that is stored within the floating gate. To actually use a memory cell, each state thereof is associated with a binary value.
One type of flash memory device is based on a technology commonly known as “Single Bit per Cell” (SBC), which means that each memory cell in an SBC memory device stores one bit. Storing one bit per cell means that the cell is configured to be in (i.e., to store) one of two possible states. Typically, one state of the cell is associated with zero charge being stored in the cell's floating gate. This state is the “unwritten” state of the cell and, usually, it represents the binary digit “1”. The cell's other state typically is associated with some amount of negative charge in the floating gate. This state is the “written” state of the cell and, usually, it represents the binary digit “0”. The existence of negative charge in the floating gate results in an increase in the threshold voltage of the cell's transistor and, consequently, in the voltage that has to be applied to the transistors control gate in order to cause the transistor to conduct.
Flash memory devices are capable of performing three operations: writing (often called “programming” for historical reasons) data into memory cells, reading data from memory cells, and erasing data from memory cells. These operations are initiated by an external host device but handled locally by a controller. Writing a binary digit (i.e., “0” or “1”) into a memory cell involves changing the charge in the transistor's floating gate to thereby change the threshold voltage of the cell. Reading a binary digit stored in a memory cell involves checking the level of the threshold voltage of the cell—if the threshold voltage is in the higher state, then the bit value is interpreted as logical value “0”. If, however, the threshold voltage is in the lower state, then the bit value is interpreted as logical value “1”. Actually, there is no need to accurately read the cell's threshold voltage. Instead, it is adequate to correctly identify which of the two states the cell is currently in. To accomplish that, the threshold voltage of the cell has to be compared to a reference voltage whose value is between the two states, and to determine if the cell's threshold voltage is either below or above the reference value.
For many types of flash memories, for example NAND flash memories, writing and erasing operations cannot be done on individual memory cells but, rather, they are done on groups of memory cells. Writing operations are done on “pages”, which are relatively small (typically 512 bytes, 2 Kbytes, or 4 Kbytes for a NAND flash memory device), whereas erasing operations are done on “blocks”, which are larger than pages (typically 32 Kbytes or 128 Kbytes for a NAND flash memory device).
Another type of flash memory devices is based on a technology commonly known as “Multi Bit per Cell” (MBC). In an MBC memory device each memory cell stores N bits (N≧2), which means that an MBC memory cell is configured to store 2N states. For example a memory cell that stores 2 bits stores four states, each of which is associated with one of the four binary values “00”, “01”, “10”, and “11”.
As a cell's state is represented by a threshold voltage of the cell, an MBC cell storing two bits supports four distinct ranges of the cell's threshold voltage. As for the SBC cell, each state of an MBC cell is actually a voltage range and not a single voltage. When reading the cell's content (i.e., the stored binary value), the cell's threshold voltage must be correctly associated with the correct voltage range. An MBC flash device is discussed, for example, in U.S. Pat. No. 5,434,825 to Harari.
When the concept of flash memory technologies was first conceived, MBC NAND flash devices were relatively rare and SBC devices were the norm. Therefore, traditional designs of hosts that utilize flash memory technologies are SBC-oriented, which render them incompatible with MBC devices. Therefore, even though the MBC NAND technology has matured, is more cost effective than SBC devices (at least in terms of megabytes per dollar) and is already available in the market, MBC-based NAND devices cannot be used by SBC-compliant host devices, which impedes further proliferation of the MBC technology even though MBC devices offer more storage capacity per same physical area than SBC devices. Even if memory cells, which store data using the same number of bits-per-cell are involved, other technical mismatches may exist if storage devices are supplied by different storage vendors because there is no standard for NAND interfaces and different vendors may and do use different kinds of NAND interfaces.
Overcoming this compatibility problem (i.e., making MBC flash devices and SBC-compliant hosts able to interact with each other) is not trivial because SBC devices and MBC devices inherently differ in several technical aspects. For example, SBC devices and MBC devices utilize data pages and data blocks of different sizes. In addition, because the voltage spacing (an “error margin”) between the two states of an SBC cell is larger than the error margin existing between each two adjacent states of an MBC, an SBC cell offers a higher level of reliability, for which reason SBC cells are usually used for booting computer systems. To compensate for their relatively lower reliability, MBC devices use stronger error correction schemes, for example a stronger Error Correction Code (ECC).
As SBC flash memory devices offer higher reliability and faster responsiveness, efforts have been made to combine SBC capabilities with MBC's. However, those efforts are directed towards improving only specific technical aspects of the MBC flash memory device. Some prior art addresses the booting aspect; i.e., they offer storing an initialization (i.e., booting) program in a specific area in an MBC flash memory device to obtain booting reliability that is similar to the reliability offered by “genuine” SBC technology. Other prior art addresses the reliability aspect and provides a stronger error correction mechanism. Other prior art address the responsiveness speed aspect and permit dedicating and using SLC caching in the MBC device, and so on. However, the prior art does not teach writing SBC data into an MBC flash memory device as regular MBC data, or reading SBC data from within MBC data.